The present invention relates to a CMOS basic cell and a method for fabricating a gate array semiconductor integrated circuit using the basic cell.
Recently, semiconductor integrated circuits are more and more highly developed in their integration and performance in accordance with refinement of processes, and the cost and period required for the development are steadily increasing accordingly. Under such circumstances, gate arrays, which can be designed by merely modifying interconnect patterns with CAD (computer-aided design) or the like, are widely used as a method for fabricating semiconductor integrated circuits suitable for reducing the cost and period required for the development or for few-of-a-kind production.
In general, a gate array is fabricated as follows: A basic cell having a previously determined layout pattern and an interconnect pattern of a logic cell using one or more basic cells are prepared, the basic cells are automatically placed and automatically connected to each other with interconnects by using the CAD or the like.
FIG. 30 shows the structure of a conventional CMOS basic cell composed of four transistors. In FIG. 30, a reference numeral 1 denotes a CMOS basic cell. In the basic cell 1, a first P-channel transistor TP1 includes a gate electrode 2A placed in a U shape in a plane view and dopant diffusion layers 3A and 4A provided on both sides of the gate electrode 2A. The dopant diffusion layers 3A and 4A work as the source and the drain. A second P-channel transistor TP2 includes a gate electrode 5A placed in a U shape facing a reverse direction to the gate electrode 2A of the transistor TP1, a dopant diffusion layer 6A provided on one side of the gate electrode 5A, and the dopant diffusion layer 4A shared with the transistor TP1. A first N-channel transistor TN1 includes a gate electrode 2B placed in a U shape in a plane view and dopant diffusion layers 3B and 4B provided on the both sides of the gate electrode 2B. The dopant diffusion layers 3B and 4B work as the source and the drain. A second N-channel transistor TN2 includes a gate electrode 5B placed in a U shape facing a reverse direction to the gate electrode 2B of the transistor TN1, a dopant diffusion layer 6B provided on one side of the gate electrode 5B and the dopant diffusion layer 4B shared with the transistor TN1. Furthermore, reference numerals 7 and 8 denote global power supply pattern and GND (ground) pattern provided in upper and lower portions in the drawing by using a first interconnect layer.
In FIG. 30, broken lines drawn in the basic cell 1 denote wiring grids. A wiring grid herein means a place where an interconnect pattern of a logic cell is disposed as a wiring track. The wiring grids are disposed so as to cross the gate electrodes 2A, 2B, 5A and 5B and the dopant diffusion layers 3A, 3B, 4A, 4B, 6A and 6B, the power supply pattern 7 and the GND pattern 8 of the basic cell 1, and the interval thereof is determined in accordance with a placement pitch of the transistors or an interconnect pitch determined based on the semiconductor process rule.
At a stage of design of a logic cell, wiring is optionally determined to place on the wiring grids, and at a stage of design of a semiconductor integrated circuit using a plurality of logic cells, the interconnects are placed on the wiring grids by using a CAD system or the like. At these design stages, in the case where, for example, a second interconnect layer is used for wiring, the interconnect pitch of the second layer is generally set to the same pitch as that of a first layer for easing connection to interconnects of the first layer. The interconnect pitch is similarly determined also in the case where a third or upper interconnect layer is used for wiring. In FIG. 30, the number of wiring tracks of the basic cell 1 extending in the X-direction is 11 and the number of wiring tracks extending in the Y-direction is 3.
The conventional basic cell, however, has the following problem: For example, when a circuit example of a DFF (D flip-flop) shown in FIG. 2A is constructed by using the basic cell of FIG. 30, if interconnects of the first and second layers are used for the interconnects of the logic cell, a layout structure of FIG. 31A or FIG. 31B is obtained. The number of interconnect layers used in this case are three in total, that is, the first and second interconnect layers and a layer of vias for connecting the first interconnect layer to the second interconnect layer.
Alternatively, when the interconnects of the second layer alone are used for the interconnects of the logic cell with the interconnects of the first layer used as fixed interconnects as disclosed in, for example, Japanese Laid-open Patent Publication No. 1-270329, a layout structure of FIG. 32 is obtained. The number of interconnect layers used in this case is also three in total, that is, the interconnects of the second layer and the interconnects of the upper third layer, which are necessary because the interconnects are crowded, and a layer of vias for connecting the second interconnect layer to the third interconnect layer.
Vias for connecting a gate electrode and a dopant diffusion region to the interconnects of the first layer are naturally necessary not only in the basic cell of FIG. 30 and the exemplified circuit configurations shown in FIGS. 31A and 31B but also every example described below. However, the vias are not directly concerned with the essence of the invention and hence are herein neither described nor shown in drawings. FIG. 2B is a symbol diagram of the DFF of FIG. 2A, and FIG. 2C is an operation timing chart. In FIG. 2B, a reference numeral 100 denotes a DATA input terminal, a reference numeral 110 denotes a CLK input terminal, a reference numeral 120 denotes an inverted CLK input terminal, a reference numeral 200 denotes a DATA output terminal, and a reference numeral 210 denotes an inverted DATA output terminal.
Layout structures of other logic cells obtained by using the conventional basic cell are as follows: FIG. 33 shows a layout structure of a buffer circuit example of FIG. 4A constructed by using the basic cell of FIG. 30 with interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of FIG. 34 is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 35 shows a layout structure of an ORNAND circuit of FIG. 6A constructed by using the basic cell of FIG. 30 with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of FIG. 36 is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 37 shows a layout structure of a selector circuit of FIG. 8A constructed by using the basic cell of FIG. 30 with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of FIG. 38 is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
FIG. 39 shows a layout structure of an SRAM circuit of FIG. 25A constructed by using the basic cell of FIG. 30 with the interconnects of the first and second layers used as the interconnects for the logic cell. Alternatively, a layout structure of FIG. 40 is obtained when the interconnects of the second layer alone are used as the interconnects for the logic cell with the interconnects of the first layer used as fixed interconnects.
As described above, two interconnect layers are necessary for interconnects for a logic circuit in forming, by using the conventional basic cell of FIG. 30, any of a logic circuit having a clock signal line like a DFF, a logic circuit including transistors connected in parallel like a buffer circuit, a composite logic circuit such as an ORNAND circuit, a logic circuit having a control signal line like a selector circuit and a logic circuit for a memory like an SRAM. As a result, the wiring tracks for upper interconnects are consumed, which increases the line crowdedness in the design of a semiconductor integrated circuit. Accordingly, the ratio of used gates to all the gates in the gate array is lowered, so as to cause a problem that the degree of integration of the semiconductor integrated circuit is lowered. Furthermore, in the case where it is necessary to modify logic or wiring, three layers in total, that is, two layers for interconnects and one for vias, are necessary for the modification. This can be an obstacle to reduction of the cost and period required for development, which is originally the largest advantage of a gate array.
In the case where a D flip-flop circuit having a scanning function as shown in FIG. 20A is constructed by using the basic cell of FIG. 30, a layout structure of FIG. 41 is obtained when the interconnects of the first and second layers are used as the interconnects for the logic cell. When a semiconductor integrated circuit is constructed by using three D flip-flop circuits DFF1 through DFF3 having a scanning function and a combinational logic circuit LC as shown in FIG. 20C, a scan chain method is generally employed in which the output terminal Q of the D flip-flop circuit at the front stage (for example, DFF1) is connected to the scan data input terminal DT of the D flip-flop circuit at the back stage (for example, DFF2) through an interconnect L. FIG. 20D is a timing chart of a general operation employed in this case, and FIG. 20E is a timing chart of a scan operation. In the general operation, a data output from the output terminal Q of the D flip-flop circuit at the front stage is transferred through the combinational logic circuit LC to the data input terminal D of the D flip-flop circuit at the back stage. Therefore, the D flip-flop circuit at the back stage has sufficient hold time for the data. In contrast, in the scan operation, an output data from the output terminal Q of the D flip-flop circuit at the front stage is transferred through the interconnect L alone to the scan data input terminal DT of the D flip-flop circuit at the back stage. Therefore, transfer delay time of the scan data is too short to attain sufficient hold time, which can easily cause a hold error of the scan data. Accordingly, the length of the interconnect L is increased to elongate the line delay time.
However, in the case where the D flip-flop circuit having a scanning function is formed by using the conventional basic cell of FIG. 30, two interconnect layers in total, that is, the first interconnect layer and the second interconnect layer, are necessary for adjusting the delay. Furthermore, there is a difference in the delay per unit length of the interconnect between the first interconnect layer and the second interconnect layer, and hence, it takes time to design for the adjustment of the line delay. These disadvantages can be an obstacle to the reduction of the cost and development period, which is the largest advantage of a gate array.
U.S. Pat. No. 5,814,844 discloses the following structure of a CMOS basic cell: Auxiliary interconnects used in connecting gate electrodes to each other or a gate electrode to a diffusion region within the basic cell are previously disposed in a polysilicon layer where the gate electrodes are formed (hereinafter referred to as the gate layer). When, for example, a gate electrode and a diffusion region included in the basic cell are necessary to connect to each other, an interconnect connected to the gate electrode and an interconnect connected to the diffusion region are disposed in an interconnect layer above the gate electrode, and these interconnects are connected to the auxiliary interconnect through two via contacts. However, the auxiliary interconnects are disposed in the gate layer and used for connecting the gate electrodes to each other or a gate electrode to a diffusion region within the basic cell, and are not used as part of global interconnects for connecting, for example, gate electrodes of two basic cells to each other.
The speed and consumption power of the DFF are restricted by the line length or the parasitic capacitance determined in accordance with the size and the structure of the basic cell. For increasing the speed and reducing the consumption power without changing the size of the basic cell itself, for example, Japanese Laid-Open Patent Publication No. 07-240501 discloses a technique of lowering diffusion capacitance by reducing the area of a diffusion region to be smaller than a contact region in portions other than the contact region. This technique, however, has a problem that the number of wiring tracks is reduced, and for overcoming this problem, it is necessary to modify the process for securing the wiring tracks.
Furthermore, for example, Japanese Laid-Open Patent Publication No. 09-181284 discloses a technique of reducing signal transfer delay time for increasing the speed by overlapping contact regions of adjacent basic cells. This technique also has the problem that the number of wiring tracks is reduced.
An object of the invention is providing a CMOS basic cell capable of realizing a desired logic circuit by using merely one interconnect layer or preventing a hold error of a flip-flop circuit having a scan test function without increasing the area of the basic cell, and a method for fabricating a semiconductor integrated circuit using the CMOS basic cell.
Another object of the invention is providing a CMOS basic cell capable of increasing operation speed and reducing consumption power by reducing the layout area of the basic cell with securing sufficient wiring tracks, and a method for fabricating a semiconductor integrated circuit by using the CMOS basic cell.
Specifically, in the case where a semiconductor integrated circuit is constructed by arranging a plurality of CMOS basic cells in parallel, an interconnect layer is provided for global routing above these basic cells. Therefore, in order to achieve the object, according to the invention, an interconnect pattern is previously formed in an interconnect layer directly below this interconnect layer for global routing (namely, in an uppermost interconnect layer of each CMOS basic cell), so that the previously formed interconnect pattern can be also used for connecting the basic cells to one another through the global routing.
Also, in order to achieve the other object, the gate and the diffusion region of an N-channel transistor or a P-channel transistor are formed in specific shapes in the present invention, so as to reduce the layout area of a semiconductor integrated circuit constructed by arranging a plurality of basic cells.
Specifically, the first CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; and an interconnect pattern extending along a direction perpendicular to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region, and the interconnect pattern is formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
The second CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; and an interconnect pattern extending along a direction parallel to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region, and the interconnect pattern is formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
The third CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; and an interconnect pattern extending along a direction parallel to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region to be used for connection to an interconnect pattern of another adjacent basic cell, and the interconnect pattern is formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
The fourth CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; an interconnect pattern extending along a direction perpendicular to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region; and another interconnect pattern extending along a direction parallel to the boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region, and the interconnect patterns are formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
The fifth CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; an interconnect pattern extending along a direction parallel to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region; and another interconnect pattern extending along the direction parallel to the boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region to be used for connection to an interconnect pattern of another adjacent basic cell, and the interconnect patterns are formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
The sixth CMOS basic cell of this invention comprises an N-channel transistor region and a P-channel transistor region isolated from each other by an insulating film on a semiconductor substrate; an interconnect pattern extending along a direction perpendicular to a boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region; and another interconnect pattern extending along a direction parallel to the boundary between the N-channel transistor region and the P-channel transistor region and provided independently of the N-channel transistor region and the P-channel transistor region to be used for connection to an interconnect pattern of another adjacent basic cell, and the interconnect patterns are formed in an uppermost interconnect layer among one, two or more interconnect layers of the CMOS basic cell.
Any of the first through sixth CMOS basic cells of this invention can further comprise a fixed interconnect region where a power supply interconnect and a ground interconnect are provided, and the interconnect pattern is provided in the fixed interconnect region.
The method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of any of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a logic circuit including a clock signal line by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of any of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a logic circuit including transistors connected to each other in parallel by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of any of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a compound logic circuit by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of any of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a logic circuit including a control signal line by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a logic circuit for a memory by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells and additional interconnect layers respectively provided above the basic cells, comprises the steps of arranging a plurality of the first through sixth CMOS basic cells on a semiconductor substrate; and realizing a flip-flop circuit having a scan test function by using the interconnect patterns formed in the uppermost interconnect layers of the CMOS basic cells and the additional interconnect layers.
The seventh CMOS basic cell of this invention to be used with other basic cells having the same structure disposed on right and left hand sides thereof, comprises an N-channel transistor and a P-channel transistor formed on a semiconductor substrate, and a gate of at least one of the N-channel transistor and the P-channel transistor is in a hooked shape having a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in the other sideward direction at a lower portion thereof.
The eighth CMOS basic cell of this invention to be used with other basic cells having the same structure disposed on right and left hand sides thereof, comprises an N-channel transistor and a P-channel transistor formed on a semiconductor substrate, and a diffusion region of at least one of the N-channel transistor and the P-channel transistor is in a hooked shape having a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in the other sideward direction at a lower portion thereof.
The ninth CMOS basic cell of this invention to be used with other basic cells having the same structure disposed on right and left hand sides thereof, comprises an N-channel transistor and a P-channel transistor formed on a semiconductor substrate, and a gate of at least one of the N-channel transistor and the P-channel transistor is in a hooked shape including a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in the other sideward direction at a lower portion thereof, and a diffusion region of at least one of the N-channel transistor and the P-channel transistor is in a hooked shape having a first bent part bending in one sideward direction at an upper portion thereof and a second bent part bending in the other sideward direction at a lower portion thereof.
In the ninth CMOS basic cell, a first N-channel transistor and a first P-channel transistor are formed to extend along a vertical direction, a second N-channel transistor is disposed on a side of the first N-channel transistor and a second P-channel transistor is disposed on a side of the first P-channel transistor, and a gate of each of the first and second N-channel transistors and the first and second P-channel transistors is formed in the hooked shape.
In the ninth CMOS basic cell, the gates of the first and second N-channel transistors are disposed in a manner that the first bent part of one gate overlaps the second bent part of the other gate when seen along the vertical direction from one position in a horizontal direction, and the gates of the first and second P-channel transistors are disposed in a manner that the first bent part of one gate overlaps the second bent part of the other gate when seen along the vertical direction from one position in the horizontal direction.
In the ninth CMOS basic cell, the first and second N-channel transistors share one diffusion region and the first and second P-channel transistors share one diffusion region, each of the diffusion regions is divided into a shared diffusion region shared by the first and second N-channel or P-channel transistors and positioned between the gates of the first and second N-channel or P-channel transistors; a first dedicated diffusion region positioned on a side of the gate of the first N-channel or P-channel transistor opposite to the shared diffusion region; and a second dedicated diffusion region positioned on a side of the gate of the second N-channel or P-channel transistor opposite to the shared diffusion region, the first bent part is formed in the first dedicated diffusion region, and the second bent part is formed in the second dedicated diffusion region.
Any of the seventh through ninth CMOS basic cells, can comprise, outside of a transistor region where the N-channel transistor and the P-channel transistor are disposed, a fixed interconnect region where a power supply interconnect and a ground interconnect are disposed.
Alternatively, the method of this invention for fabricating a gate array semiconductor integrated circuit including a plurality of basic cells arranged in a horizontal direction, comprises a step of arranging a plurality of any of the seventh through ninth CMOS basic cells in the horizontal direction in a manner that the first bent part of one CMOS basic cell overlaps the second bent part of another adjacent CMOS basic cell when seen along a vertical direction from one position in a horizontal direction.
Accordingly, in the present invention, in fabricating a gate array semiconductor integrated circuit by using a plurality of CMOS basic cells, the interconnect pattern previously formed in the uppermost interconnect layer of each CMOS basic cell is used as a part of the interconnects for connecting the basic cells to one another. Therefore, even a logic circuit with a complicated structure can be fabricated and realized by using merely one interconnect layer for wiring. Accordingly, the line crowdedness in the interconnect layer used in wiring during the design of the semiconductor integrated circuit can be reduced, so as to improve the ratio of used gates to all the gates in the gate array, resulting in improving the degree of integration of the semiconductor integrated circuit.
Furthermore, in the present CMOS basic cell and the fabrication of a semiconductor integrated circuit by arranging a plurality of CMOS basic cells, the gate of the N-channel or P-channel transistor of each basic cell is formed in the hooked shape. In the case where the semiconductor integrated circuit is constructed by arranging the plural basic cells in the horizontal direction, the basic cells are disposed so as to partly overlap in a manner that the portion in the hooked shape is inlaid with the portion in the hooked shape of the adjacent basic cell. Accordingly, the layout area of the semiconductor integrated circuit can be effectively reduced. In addition, owing to this overlap arrangement, in the case where the gate of the transistor of one basic cell is connected to the diffusion region of the transistor of another adjacent basic cell, the interconnect therebetween can be disposed to extend in the vertical direction in the same position along the horizontal direction, and there is no need to extend the interconnect in the horizontal direction. Accordingly, the line length can be reduced. As a result, the layout area can be reduced with sufficiently securing the wiring tracks, and in addition, the operation speed can be increased and power consumption can be reduced due to the reduced line length and reduced diffusion capacitance.